Diagram Guide

This is a simple Buffer 50Mhz Trigger Circuit Diagram, This has a stable trigger 100 m V sensitivity at 50 MHz. The FETs comprise a simple high-speed buffer and the LT1016 compares the buffer`s output to the potential at tbe trigger level potentiometer, which can be of either polarity. The 10-KO resistor provides hysteresis, eliminating `chattering`` caused by noisy input signals. To calibrate this schema, ground the input and adjust the input zero control for 0 V at Q2`s drain terminal.Read: Stabilized Capacitance Buffer Circuit Diagram